In most Class-D amplifiers some form of pulse-width modulation (PWM) is applied. A PWM signal can be constructed feed-forward by simply comparing the input signal Vsig with a triangular reference wave Vref as shown in FIG. 1. Usually the frequency of the reference wave Vref is much higher than that of the input signal Vsig.
Ideally, the spectrum of the PWM signal does not contain harmonics of the modulating signal, which means it can be considered ideal in terms of distortion. However, this is only true if the reference wave Vref has sufficient linearity, i.e. the slopes of the reference wave Vref need to be perfectly straight.
Many Class-D amplifiers use an integrating feedback loop to provide power supply rejection and correction of switching errors in the output stage. An example of such a feedback loop is shown in FIG. 2. The operation of this loop is described in detail in Berkhout, M. “An Integrated 200W Class-D Audio Amplifier”, IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1198-1206, July. 2003, [1], which is herewith incorporated in the application by reference. The loop has two integrators configured around amplifiers gm1 and gm2. The two integrators realize a second-order loop transfer. The output signal VPWM of the amplifier is a square wave pulse-width modulated (PWM) signal. The load RO is connected to the amplifier by means of a low-pass LC-filter (L0, C0). The output voltage VPWM is converted to a current IPWM by feedback resistor R1 and injected into the virtual ground of the first integrator gm1. This yields a triangular wave V1 at the output of the first integrator gm1. A reference clock signal osc is converted to a square wave current Iosc that is injected into the virtual ground of the second integrator gm2. This yields a second (reference) triangular wave V2 at the output of the second integrator. The triangular wave signals V1 and V2 are fed to the non-inverting and inverting inputs of a comparator A0. When the triangular waves intersect the comparator output pwm changes state and the output VPWM of the amplifier switches yielding the desired PWM signal. Note that the peaks of signal V2 coincide with the edges of signal osc and the peaks of signal V1 coincide with the edges of signal pwm. The input signal VI is converted to a current IIN by V-I converter gm0 and injected into the virtual ground of the first integrator gm1.
FIG. 3(a) shows the triangular wave signals V1 and V2 at zero input yielding a 50% PWM duty-cycle (see signal pwm). FIG. 3(b) shows the same signals when a negative input signal is applied. The input signal causes the slopes (and amplitude) of V1 to change. The shape of V2 remains (almost) the same but the DC-level is shifted with respect to zero. The output signal pwm of the comparator now has a duty-cycle smaller than 50%. The opposite happens for a positive input signal as shown in FIG. 3(c) (see signal pwm). In this manner a linear relation is realized between the input signal and the duty-cycle of the output signal VPWM. In FIGS. 3(a) to 3(c) the oscillator signal is designated with reference sign osc.
The loop transfer Aβ of the feedback loop shown in FIG. 2 is shown in FIG. 4. At low frequencies the loop transfer has a second order behaviour. At higher frequencies the second integrator gm2 is by-passed by the direct path from the first integrator gm1. This creates a zero in the loop transfer at the unity-gain frequency of the second integrator: ωz=1/R2C2.
The zero causes the loop transfer to have a first order behaviour near the unity gain frequency ωug of the loop. As is explained in [1] the unity gain frequency ωug is coupled to the PWM switching frequency ωpwm by a factor π.
In current implementations the capacitors used in the integrators are required to be linear. This requirement is essentially a continuation of the linearity requirement of the reference wave Vref in feed-forward PWM generation described above. Unfortunately linear capacitors in IC processes tend to be large. Usually such capacitors are realized by exploiting the capacitance between metal-interconnect layers resulting in a relatively low capacitance per area. Gate-oxide capacitors on the other hand have high capacitance per area but suffer from non-linearity. Non-linearity of capacitors in the integrators not only distorts the (triangular) output signals of the integrators but also influences the frequency of the poles and zeros in the feedback loop. In a typical IC process the ratio in area between a linear metal-interconnect capacitor and a non-linear gate-oxide capacitor can easily be as high as a factor of twelve. Consequently, the use of linear capacitors constitutes a significant part of the total area of the circuit.